Non-volatile memory device and fabrication method thereof

ABSTRACT

A nonvolatile read-only memory device, wherein a word line is on a substrate and the word line includes a metal layer a polysilicon line. A trapping layer is further located between the word line and the substrate. A polysilicon protection line is formed over the substrate and the polysilicon protection line connects the word line and a grounded doped region in the substrate, wherein the resistance of the polysilicon protection line is higher than that of the word line.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the priority benefit of Taiwanapplication serial no. 91105279, filed on Mar. 20, 2002.

BACKGROUNDING OF THE INVENTION

[0002] 1. Field of Invention

[0003] The present invention relates to a read-only memory device andthe fabrication method thereof. More particularly, the present inventionrelates to a non-volatile read only memory device and the fabricationmethod thereof.

[0004] 2. Description of Related Art

[0005] The current fabrication method for a non-volatile read onlymemory device comprises forming a trapping layer on a substrate, whereinthe trapping layer is a stacked structure formed with a siliconoxide/silicon nitride/silicon oxide (ONO) composite layer. A read onlymemory device that uses an ONO composite layer as the trapping layer isknown as a nitride read only memory (NROM). A polysilicon gate is thenformed on the ONO layer, followed by forming a source region and a drainregion on both sides of the ONO layer in the substrate.

[0006] The plasma used in the fabrication of a NROM causes a chargebuild-up on metal. This phenomenon is known as the “antenna effect”.When a transient charge imbalance occurs, charges are injected into theONO layer inducing a programming effect, leading to the problem of ahigh threshold voltage. In general, the threshold voltage varies in awild range of 0.3 V to 0.9 V.

[0007] Conventionally, the method to prevent the programming problemresulted from the antenna effect is to form a diode in the substrateconnecting electrically with the word line. As the transient chargesreach a specific value, the device is discharged by the electricbreakdown of the diode. However, when the voltage induced by the chargesis less than the breakdown voltage of the diode, the charges may stillbe injected into the ONO layer to induce the programming effect. Inaddition, such a design lowers the input voltage of the device anddecreases the rate of the writing operation.

SUMMARY OF THE INVENTION

[0008] The present invention provides a non-volatile read only memoryand the fabrication method thereof, wherein the plasma induced damageson a memory device are prevented.

[0009] The present invention provides a non-volatile read only memoryand the fabrication method thereof, wherein the transient chargeimbalance is obviated to prevent electric charges to be injected intothe ONO layer, inducing the programming effect.

[0010] The present invention provides a non-volatile read only memoryand the fabrication method thereof, wherein a high threshold voltage isprevented.

[0011] The present invention provides a non-volatile read only memoryand the fabrication method thereof in which the programming problem dueto the antenna effect, leading to a lower input voltage and a decreasein the rate of the writing operation is resolved

[0012] Accordingly, the present invention provides a non-volatile readonly memory, wherein a word line is formed over a substrate, and theword line includes a metal layer and a polysilicon line. A trappinglayer is located between the word line and the substrate. Moreover, thenon-volatile read only memory further comprises a polysilicon protectionline formed over the substrate. The polysilicon protection lineelectrically connects the word line and the grounded doped region in thesubstrate, wherein the resistance of the polysilicon protection line ishigher than that of the word line.

[0013] The present invention provides another fabrication method for anon-volatile read only memory, wherein a non-volatile read only memorycell is formed on a substrate. A polysilicon protection line is furtherformed on the substrate. The polysilicon protection line and the wordline of the non-volatile read only memory cell are connected, whereinthe resistance of the polysilicon protection line is higher than that ofthe word line. Thereafter, a grounded doped region is formed in thesubstrate, followed by forming a contact on the substrate such that thecontact connects the grounded doped region and the polysiliconprotection line. A metal interconnect is then formed on the substrate.Subsequent to fab-out, a high voltage is applied to burn out thepolysilicon protection line.

[0014] The present invention further provides another fabrication methodfor a non-volatile read only memory device, wherein a substratecomprising an isolation region is provided. A trapping layer is thenformed on the substrate. After this, a polysilicon layer and a silicidelayer are sequentially formed on the substrate. The above layers arefurther patterned to form a word line for the non-volatile read onlymemory and a polysilicon line. The thickness of a portion of thepolysilicon line is reduced to form a polysilicon protection line abovethe isolation region. Thereafter, a dielectric layer is formed on thesubstrate to cover the above devices. A first contact and a secondcontact that connect the silicide layer and a doped region in thesubstrate are further formed in the dielectric layer. After thecompletion of the fabrication process, a high current is applied to burnout the polysilicon protection line.

[0015] The present invention provides a fabrication method for anelectrically connected polysilicon protection line with the substrate toguide the charges built up in a fabrication process to the substrate.Damages induced to the ONO layer of the non-volatile memory device andthe programming effect are thus prevented. Subsequent to fab-out, a highcurrent is used to burn out the polysilicon protection line, allowingthe memory device to operate normally. The transient imbalance chargesare discharged through the substrate to prevent the problems encounteredin a high threshold voltage due to the trapping of charges in the ONOlayer.

[0016] Since the resistance of the polysilicon protection line is higherthan that of the word line, the polysilicon protection line is burnt outby using a high current after the manufacturing process is completed.Therefore, the input voltage is prevented from being lower to slow downthe rate of the writing operation during a normal operation of thememory device.

[0017] It is to be understood that both the foregoing generaldescription and the following detailed description are exemplary, andare intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention. In the drawings,

[0019]FIGS. 1A to 1E illustrate a process flow of fabricating anon-volatile read only memory according to a first aspect of thisinvention in a cross-sectional view;

[0020]FIGS. 2A to 2B illustrate a process flow of forming a polysiliconline and a silicide word line during the fabrication a non-volatile readonly memory according to a second aspect of this invention in a top viewand in a cross-sectional view, respectively;

[0021]FIGS. 3A to 3B illustrate a process flow of forming a polysiliconprotection layer during a fabrication of a non-volatile read only memoryaccording to the second aspect of this invention in a top view and in across-sectional view, respectively; and

[0022]FIGS. 4A to 4B illustrate a process flow of forming aninterconnect during a fabrication of a non-volatile read only memoryaccording to the second aspect of this invention in a top view and in across-sectional view, respectively.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] The present invention provides a fabrication method for anon-volatile read only memory device that prevents the plasma-generatedantenna effect during the fabrication of the non-volatile read onlymemory.

[0024]FIGS. 1A to 1E illustrate a process flow of fabricating thenon-volatile read only memory according to a first aspect of thisinvention in a cross-sectional view.

[0025] As shown in FIG. 1A, a non-volatile read only memory cell 102 isformed on a substrate 100. The non-volatile read only memory cell 102includes a trapping layer 104 and a word line 106 thereon, wherein thetrapping layer 104 includes a stacked structure of a siliconoxide/silicon nitride/silicon oxide (ONO) composite layer. The word line106 includes a polysilicon line 105 a and a metal layer 105 b, whereinthe metal layer 105 b includes tungsten silicide (WSi_(x)). Thesubstrate 100 further comprises an isolation region 108 that separatesthe memory cell region and the peripheral circuit region. The isolationregion 108, for example, a field oxide layer.

[0026] Continuing to FIG. 1B, a polysilicon protection line 110 isformed on the substrate 100, wherein the polysilicon protection line 110is connected with the word line 106 of the non-volatile memory cell 102.The resistance of the polysilicon protection line 110 is higher thanthat of the word line 106. In other words, the resistance of thepolysilicon protection line 110 is higher than the resistance of thepolysilicon line 105 a of the word line 106. Moreover, the polysiliconprotection line 110 is extended to the peripheral circuit region throughthe isolation region 108.

[0027] Thereafter, as shown in FIG. 1C, a grounded doped region 112 isformed in the substrate 100 in the peripheral circuit region, wherein atleast a portion of the polysilicon protection line 110 is formed abovethe grounded doped region 112.

[0028] Referring to FIG. 1D, a dielectric layer 114 is formed on thesubstrate 100, and a contact 116 is formed in the dielectric layer 114,wherein the contact 116 is connected to the grounded doped region 112and the polysilicon protection line 110.

[0029] After this, as shown in FIG. 1E, a metal interconnect 118 isformed on the substrate 100. A high current is then applied to burn outthe polysilicon protection line 110 after the completion of thefabrication process, and the burnt out region 120 isolate the memorycell region and the peripheral circuit region. As a result, during theoperation of the memory device, the input voltage is prevented frombeing lowered to reduce the rate of the writing operation by thepolysilicon protection line 110.

[0030] The present invention provides a second aspect of fabricatinganother type of non-volatile read only memory, as shown in FIGS. 2A, 2B,3A, 3B, 4A and 4B.

[0031] As shown in FIGS. 2A and 2B, a substrate 200 that comprises afield oxide layer as an isolation region 202 is provided. A trappinglayer 204 is then formed on the substrate 200, wherein the trappinglayer 204 includes a stacked structure of a silicon oxide/siliconnitride/silicon oxide (ONO) composite layer. After this, a polysiliconlayer and a silicide layer are sequentially formed on the substrate 200,followed by patterning the above layers to form the word line 208 of thenon-volatile read only memory and the underlying polysilicon line 206,wherein the width of the patterned polysilicon line 206 and word line208 above the isolation region 202 is smaller than that above otherregion. The word line 208 includes tungsten silicide (WSi_(x)).

[0032] Referring to FIGS. 3A and 3B, a patterned photoresist layer 210is then formed on the substrate 200, wherein a portion of the word line208 located above the isolation region 202 is exposed. After this, usingthe photoresist layer 210 as etching mask, the exposed word line 208 isremoved. The etching is continued to the polysilicon line 206 underneaththe word line 208 to reduce the thickness of the portion of thepolysilicon line 206 that is above the isolation region 202 to form apolysilicon protection line 206 a at the region 212.

[0033] Continuing to FIGS. 4A and 4B, the photoresist layer 210 isremoved followed by forming a doped region 214 in the substrate 200. Adielectric layer 216 is then formed on the substrate 200 to cover theabove various devices. Contact 218 a and contact 218 b that respectivelyconnect to the word line 208 and the doped region 214 in the substrate200 are then formed in the dielectric layer 216 followed by aninterconnect manufacturing process. The interconnect manufacturingprocess is, for example, forming a metal interconnect 220 on thedielectric layer 216 and the metal interconnect 220 connects with thecontact 218 a. Subsequent to fabrication process, a high current is thenapplied to burn out the polysilicon protection line 206 a. Normally theburnt out region is the narrowest portion 212 of the polysiliconprotection line 206 a.

[0034] In accordance to the present invention, a polysilicon protectionline that is electrically connected to the substrate is used to reducethe generation of charges, even under a high pressure environment of aplasma involved process. The transient imbalance charges can bedischarged to the substrate through the polysilicon protection line toprevent damages induced on the ONO composite layer of the nonvolatilememory device or to prevent the programming effect, leading to a highthreshold voltage.

[0035] Accordingly, damages induced on the trapping layer or inducingthe programming effect are prevented through the polysilicon protectionline. Moreover, a high current is used to burn out the polysiliconprotection line subsequent to the manufacturing process to allow anormal function of the memory device.

[0036] Since the resistance of the polysilicon protection line of thepresent invention is higher than that of the word line, a high currentis used to burn out the polysilicon protection line subsequent tofab-out. Consequently, a lowering of the input voltage, leading to adecrease of the rate of the writing operation by the polysiliconprotection line of the present invention is prevented.

[0037] It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

What is claimed is:
 1. A non-volatile read only memory device,comprising: a word line formed over a substrate, wherein the word lineincludes a metal layer and a polysilicon line; a trapping layer locatedbetween the word line and the substrate; and a polysilicon protectionline formed over the substrate, the protection line electricallyconnects the word line and a grounded doped region in the substrate,wherein a resistance of the polysilicon protection line is higher thanthat of the word line.
 2. The device of claim 1, wherein the resistanceof the polysilicon protection line is higher than that of thepolysilicon line of the word line.
 3. The device of claim 1, wherein thepolysilicon protection line is connected to the grounded doped regionthrough a contact.
 4. The device of claim 1, wherein the trapping layerincludes a silicon oxide/silicon nitride/silicon oxide composite layer.5. The device of claim 1, wherein the metal layer includes tungstensilicide.
 6. The device of claim 1, wherein the polysilicon protectionline is located above an isolation region.
 7. The device of claim 6,wherein the isolation region include a field oxide layer.
 8. The deviceof claim 1, wherein at least portion of the polysilicon protection lineis formed over the grounded doped region.
 9. A fabrication method for anon-volatile read only memory device, comprising: forming a non-volatileread only memory cell on a substrate; forming a polysilicon protectionline on the substrate, the protection line is connected to a word lineof the non-volatile read only memory cell, wherein a resistance of thepolysilicon protection line is higher than that of the word line;forming a grounded doped region; and forming a contact on a substrate,the contact connects the grounded doped region and the polysiliconprotection line.
 10. The method of claim 9, wherein the method furthercomprises applying a high voltage to burn out the polysilicon protectionline
 11. The method of claim 9, wherein the polysilicon protection lineis located on the substrate above an isolation region.
 12. The method ofclaim 9, wherein at least a portion of the polysilicon protection lineis formed above the grounded doped region.
 13. A fabrication method fora non-volatile read only memory, comprising: providing a substrate, thesubstrate comprises an isolation region; forming a trapping layer on thesubstrate; forming a polysilicon layer on the substrate; forming asilicide layer on the polysilicon layer; patterning the trapping layer,the polysilicon layer and the silicide layer to form a word line and apolysilicon line, wherein a dimension of the polysilicon line and theword line above the isolation region is smaller than that above otherregion; removing the word line and a portion of the polysilicon lineabove the isolation region to form a polysilicon protection line,wherein a thickness of the polysilicon protection line is less than thatof the polysilicon line; forming a doped region in the substrate;forming a first contact on the substrate, wherein the first contactconnects the doped region and the polysilicon protection line; andforming a second contact on the substrate, wherein the second contactconnects the word line.
 14. The method of claim 13, wherein the methodfurther comprises applying a high current to burn out the polysiliconprotection line.
 15. The method of claim 13, wherein the trapping layerincludes a silicon oxide/silicon nitride/silicon oxide composite layer.16. The method of claim 13, wherein the metal layer includes tungstensilicide.
 17. The method of claim 13, wherein removing the word line andthe portion of the polysilicon line further comprising: forming apatterned photoresist layer on the substrate, the patterned photoresistlayer exposes a portion of the word line above the isolation region;etching the exposed word line using the patterned photoresist layer asan etching mask; continuously etching the polysilicon line under theword line to reduce a thickness of a part of the polysilicon line abovethe isolation region; and removing the patterned photoresist layer. 18.The method of claim 13, wherein the isolation region includes a fieldoxide layer.
 19. The method of claim 13, wherein at least a portion ofthe polysilicon protection line is formed above the doped region.